View source for 18430982. Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device simplified abstract (HUAWEI TECHNOLOGIES CO., LTD.)

=Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device=


==Organization Name==

[[:Category:HUAWEI TECHNOLOGIES CO., LTD.|HUAWEI TECHNOLOGIES CO., LTD.]]


[[Category:HUAWEI TECHNOLOGIES CO., LTD.]]

==Inventor(s)==

[[:Category:Eric Wu of Shenzhen (CN)|Eric Wu of Shenzhen (CN)]][[Category:Eric Wu of Shenzhen (CN)]]

[[:Category:Jifeng Zhu of Shanghai (CN)|Jifeng Zhu of Shanghai (CN)]][[Category:Jifeng Zhu of Shanghai (CN)]]

==Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18430982 titled 'Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device

==Simplified Explanation==

The abstract describes a chip stacked structure comprising a first chip and a second chip, with through silicon vias, redistribution layers, dielectric layers, and bonding metal blocks.

* The first chip includes a first substrate, a first functional layer, and first through silicon vias.
* The diameter of the through silicon vias close to the functional layer is greater than those close to the substrate.
* The second chip includes a second substrate and a second functional layer.
* The structure also includes a first redistribution layer, a first dielectric layer, and multiple first bonding metal blocks.

== Potential Applications ==
This technology could be applied in:
* Advanced semiconductor devices
* High-performance computing systems
* Miniaturized electronic devices

== Problems Solved ==
This technology helps in:
* Improving signal transmission efficiency
* Enhancing thermal management
* Increasing integration density

== Benefits ==
The benefits of this technology include:
* Enhanced performance
* Reduced power consumption
* Increased reliability

== Potential Commercial Applications ==
The potential commercial applications of this technology could be in:
* Data centers
* Telecommunications
* Consumer electronics

== Possible Prior Art ==
One possible prior art for this technology could be:
* Stacked chip structures with through silicon vias and redistribution layers.

=== Unanswered Questions ===

=== How does this technology impact manufacturing costs? ===
This article does not address the potential impact of this technology on manufacturing costs. It would be interesting to know if the increased complexity of the structure affects production expenses.

=== What are the environmental implications of using this technology? ===
The environmental implications of using this technology are not discussed in this article. It would be important to understand if there are any sustainability concerns related to the materials or processes involved.


==Original Abstract Submitted==

A chip stacked structure includes a first chip and a second chip. The first chip includes a first substrate, a first functional layer, and first through silicon vias. A diameter of the first through silicon via close to the first functional layer is greater than a diameter of the first through silicon via close to the first substrate. The second chip includes a second substrate and a second functional layer. The chip stacked structure further includes a first redistribution layer disposed on a side that is of the second functional layer and that is away from the second substrate, a first dielectric layer disposed between the first substrate and the first redistribution layer, and a plurality of first bonding metal blocks disposed in the first dielectric layer.



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