View source for 18419846. DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS simplified abstract (Micron Technology, Inc.)

=DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Patrick Robert Khayat of San Diego CA (US)|Patrick Robert Khayat of San Diego CA (US)]][[Category:Patrick Robert Khayat of San Diego CA (US)]]

[[:Category:Sivagnanam Parthasarathy of Carlsbad CA (US)|Sivagnanam Parthasarathy of Carlsbad CA (US)]][[Category:Sivagnanam Parthasarathy of Carlsbad CA (US)]]

[[:Category:Mustafa N. Kaynak of San Diego CA (US)|Mustafa N. Kaynak of San Diego CA (US)]][[Category:Mustafa N. Kaynak of San Diego CA (US)]]

==DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18419846 titled 'DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS

==Simplified Explanation==

The memory device described in the patent application is designed to descramble scrambled composite data by performing an XOR operation with scramble codes generated by non-linear scramblers. This process removes the scrambling from the composite data, which may consist of multiple data sets scrambled with non-linear scramblers. The scrambled data sets are typically data to be written to a NAND device at high bit per cell densities, such as MLC, TLC, QLC, PLC, etc. The memory device can be used to read the scrambled data sets that have been written in a previous programming pass.

* Memory device configured to descramble scrambled composite data
* XOR operation used to remove scrambling from the composite data
* Scramble codes generated by non-linear scramblers
* Scrambled data sets written to NAND device at high bit per cell densities
* Read scrambled data sets written in a previous programming pass

== Potential Applications ==
The technology described in the patent application could be applied in various industries such as data storage, telecommunications, and cybersecurity.

== Problems Solved ==
This technology solves the problem of efficiently descrambling scrambled composite data, particularly in high-density NAND devices.

== Benefits ==
The benefits of this technology include improved data integrity, increased data storage efficiency, and enhanced security measures for data transmission and storage.

== Potential Commercial Applications ==
The potential commercial applications of this technology include data storage devices, telecommunications equipment, and cybersecurity systems.

== Possible Prior Art ==
One possible prior art for this technology could be similar descrambling techniques used in data storage devices or telecommunications systems.

=== Unanswered Questions ===

=== How does this technology compare to existing descrambling methods in terms of efficiency and speed? ===
This article does not provide a direct comparison between this technology and existing descrambling methods in terms of efficiency and speed. It would be interesting to see a performance comparison to understand the advantages of this new approach.

=== Are there any limitations to the application of this technology in specific industries or scenarios? ===
The article does not address any limitations to the application of this technology in specific industries or scenarios. It would be helpful to know if there are any constraints or challenges that may arise when implementing this technology in certain environments.


==Original Abstract Submitted==

A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.



[[Category:G06F3/06]]
[[Category:G06F9/30]]