View source for 18418546. Attribute-Point-Based Timing Constraint Formal Verification simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

=Attribute-Point-Based Timing Constraint Formal Verification=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Co., Ltd.|Taiwan Semiconductor Manufacturing Co., Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Co., Ltd.]]

==Inventor(s)==

[[:Category:Chao-Chun Lo of Hsinchu (TW)|Chao-Chun Lo of Hsinchu (TW)]][[Category:Chao-Chun Lo of Hsinchu (TW)]]

[[:Category:Boh-Yi Huang of San Jose CA (US)|Boh-Yi Huang of San Jose CA (US)]][[Category:Boh-Yi Huang of San Jose CA (US)]]

[[:Category:Chih-yuan Stephen Yu of San Jose CA (US)|Chih-yuan Stephen Yu of San Jose CA (US)]][[Category:Chih-yuan Stephen Yu of San Jose CA (US)]]

==Attribute-Point-Based Timing Constraint Formal Verification - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18418546 titled 'Attribute-Point-Based Timing Constraint Formal Verification

==Simplified Explanation==

The present invention relates to attribute-point-based timing formal verification of ASIC and SoC designs. The method involves extracting key clock-pin-net-load-setting attributes from netlists and timing constraints, checking attribute mismatch between target and golden circuit designs, and providing feedback for design modifications.

* Efficient timing formal verification of ASIC and SoC designs:
** Extract key attributes from netlists and timing constraints
** Compare attributes between target and golden circuit designs
** Provide feedback for design or timing constraint modifications

* Potential Applications:
** Semiconductor industry for ASIC and SoC design verification
** Electronic design automation tools for improved design timing sign-off

* Problems Solved:
** Ensuring accurate timing verification in complex circuit designs
** Streamlining the design process by identifying attribute mismatches

* Benefits:
** Improved accuracy in timing verification
** Faster design iterations and modifications
** Enhanced efficiency in design timing sign-off

* Potential Commercial Applications:
** Semiconductor companies for ASIC and SoC design verification services
** Electronic design automation software providers for integrating the attribute-point-based verification method

* Possible Prior Art:
** Traditional timing verification methods based on static timing analysis
** Manual verification processes for identifying timing constraints

Questions:

1. How does the attribute-point-based timing formal verification method improve efficiency in ASIC and SoC design verification?
Answer: By extracting key attributes and comparing them between target and golden circuit designs, the method quickly identifies attribute mismatches, allowing for timely design modifications.

2. What are the potential challenges in implementing the attribute-point-based timing formal verification method in complex circuit designs?
Answer: One challenge could be ensuring the accuracy and completeness of the extracted attributes from netlists and timing constraints. Additionally, integrating this method seamlessly into existing design workflows may require adaptation and training for design teams.


==Original Abstract Submitted==

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).



[[Category:G06F30/33]]