View source for 18399205. MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE simplified abstract (Intel Corporation)

=MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Elizabeth Nofen of Phoenix AZ (US)|Elizabeth Nofen of Phoenix AZ (US)]][[Category:Elizabeth Nofen of Phoenix AZ (US)]]

[[:Category:Shripad Gokhale of Gilbert AZ (US)|Shripad Gokhale of Gilbert AZ (US)]][[Category:Shripad Gokhale of Gilbert AZ (US)]]

[[:Category:Nick Ross of Chandler AZ (US)|Nick Ross of Chandler AZ (US)]][[Category:Nick Ross of Chandler AZ (US)]]

[[:Category:Amram Eitan of Scottsdale AZ (US)|Amram Eitan of Scottsdale AZ (US)]][[Category:Amram Eitan of Scottsdale AZ (US)]]

[[:Category:Nisha Ananthakrishnan of Chandler AZ (US)|Nisha Ananthakrishnan of Chandler AZ (US)]][[Category:Nisha Ananthakrishnan of Chandler AZ (US)]]

[[:Category:Robert M. Nickerson of Chandler AZ (US)|Robert M. Nickerson of Chandler AZ (US)]][[Category:Robert M. Nickerson of Chandler AZ (US)]]

[[:Category:Purushotham Kaushik Muthur Srinath of Chandler AZ (US)|Purushotham Kaushik Muthur Srinath of Chandler AZ (US)]][[Category:Purushotham Kaushik Muthur Srinath of Chandler AZ (US)]]

[[:Category:Yang Guo of Chandler AZ (US)|Yang Guo of Chandler AZ (US)]][[Category:Yang Guo of Chandler AZ (US)]]

[[:Category:John C. Decker of Tempe AZ (US)|John C. Decker of Tempe AZ (US)]][[Category:John C. Decker of Tempe AZ (US)]]

[[:Category:Hsin-Yu Li of Chandler AZ (US)|Hsin-Yu Li of Chandler AZ (US)]][[Category:Hsin-Yu Li of Chandler AZ (US)]]

==MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18399205 titled 'MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE

==Simplified Explanation==

The electronic package described in the patent application includes a first package with a first package substrate, a first die, a first mold layer, and through mold interconnects (TMIs). It also includes a second package electrically coupled to the first package, with a second package substrate, a second die, and a solder resist layer.

* The electronic package comprises a first package with a first package substrate, a first die, a first mold layer, and through mold interconnects (TMIs).
* The electronic package also includes a second package electrically coupled to the first package, with a second package substrate, a second die, and a solder resist layer.

== Potential Applications ==
The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics.

== Problems Solved ==
This technology helps in improving the electrical coupling between different packages in an electronic device, enhancing the overall performance and reliability of the device.

== Benefits ==
The use of through mold interconnects (TMIs) and solder resist layers helps in creating a more robust and efficient electronic package, leading to better functionality and durability of electronic devices.

== Potential Commercial Applications ==
This technology could be utilized in the manufacturing of advanced electronic devices, leading to improved product performance and customer satisfaction.

== Possible Prior Art ==
One possible prior art could be the use of wire bonding or flip-chip technology for interconnecting different packages in electronic devices.

=== Unanswered Questions ===

== How does this technology compare to existing methods of package interconnection in terms of cost-effectiveness? ==
The cost-effectiveness of this technology compared to traditional methods of package interconnection is not addressed in the patent application. Further research and analysis would be needed to determine the cost implications of implementing this technology.

== What impact does the use of through mold interconnects (TMIs) have on the overall size and weight of the electronic package? ==
The patent application does not provide information on the impact of TMIs on the size and weight of the electronic package. Additional studies would be required to assess how the use of TMIs affects the form factor and weight of electronic devices incorporating this technology.


==Original Abstract Submitted==

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.



[[Category:H01L23/373]]
[[Category:H01L21/02]]
[[Category:H01L21/56]]
[[Category:H01L21/768]]
[[Category:H01L23/48]]