View source for 18386880. Multi-Threaded, Self-Scheduling Processor simplified abstract (Micron Technology, Inc.)

=Multi-Threaded, Self-Scheduling Processor=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Tony M. Brewer of Plano TX (US)|Tony M. Brewer of Plano TX (US)]][[Category:Tony M. Brewer of Plano TX (US)]]

==Multi-Threaded, Self-Scheduling Processor - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18386880 titled 'Multi-Threaded, Self-Scheduling Processor

==Simplified Explanation==

The abstract describes a self-scheduling processor that can execute instructions and provide additional functionality, such as scheduling instructions automatically in response to received work descriptor data packets.

* Processor core executes received instructions
* Core control circuit automatically schedules instructions for execution by processor core based on received work descriptor data packets
* Core control circuit schedules fiber create instruction, reserves memory space for return arguments, and generates work descriptor data packets for execution of multiple threads
* Event processing, data path management, system calls, memory requests, and new instructions are also disclosed

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### Potential Applications
- High-performance computing
- Multi-threaded applications
- Real-time processing systems

### Problems Solved
- Efficient scheduling of instructions for execution
- Improved memory management
- Enhanced performance in multi-threaded environments

### Benefits
- Increased processing efficiency
- Optimized resource utilization
- Enhanced system performance and responsiveness


==Original Abstract Submitted==

Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.



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