View source for 18345389. MULTIPLEXER simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

=MULTIPLEXER=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Co., Ltd.|Taiwan Semiconductor Manufacturing Co., Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Co., Ltd.]]

==Inventor(s)==

[[:Category:Chi-Lin Liu of New Taipei City (TW)|Chi-Lin Liu of New Taipei City (TW)]][[Category:Chi-Lin Liu of New Taipei City (TW)]]

[[:Category:Shang-Chih Hsieh of Yangmei City (TW)|Shang-Chih Hsieh of Yangmei City (TW)]][[Category:Shang-Chih Hsieh of Yangmei City (TW)]]

[[:Category:Jian-Sing Li of Hsinchu (TW)|Jian-Sing Li of Hsinchu (TW)]][[Category:Jian-Sing Li of Hsinchu (TW)]]

[[:Category:Wei-Hsiang Ma of Taipei City (TW)|Wei-Hsiang Ma of Taipei City (TW)]][[Category:Wei-Hsiang Ma of Taipei City (TW)]]

[[:Category:Yi-Hsun Chen of Hsinchu (TW)|Yi-Hsun Chen of Hsinchu (TW)]][[Category:Yi-Hsun Chen of Hsinchu (TW)]]

[[:Category:Cheok-Kei Lei of Macau MO (US)|Cheok-Kei Lei of Macau MO (US)]][[Category:Cheok-Kei Lei of Macau MO (US)]]

==MULTIPLEXER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18345389 titled 'MULTIPLEXER

==Simplified Explanation==

The abstract of the patent application describes a multiplexer circuit that consists of first and second fins extending in the X-axis direction. There are four gates (first, second, third, and fourth) that extend in the Y-axis direction and contact the first and second fins. These gates are designed to receive four data signals. Additionally, there are four more gates (fifth, sixth, seventh, and eighth) that also extend in the Y-axis direction and contact the first and second fins, as well as the fifth, sixth, seventh, and eighth gates. These gates are configured to receive four select signals. An input logic circuit provides an output at an intermediate node, and an output logic circuit provides a selected one of the four data signals at an output terminal. There is also a ninth gate that extends in the Y-axis direction and contacts the first and second fins.

* The multiplexer circuit includes first and second fins extending in the X-axis direction.
* Four gates extend in the Y-axis direction and contact the first and second fins.
* The first, second, third, and fourth gates receive first, second, third, and fourth data signals, respectively.
* Four additional gates extend in the Y-axis direction and contact the first and second fins, as well as the fifth, sixth, seventh, and eighth gates.
* The fifth, sixth, seventh, and eighth gates receive the first, second, third, and fourth select signals, respectively.
* An input logic circuit provides an output at an intermediate node.
* An output logic circuit provides a selected one of the first, second, third, and fourth data signals at an output terminal.
* A ninth gate extends in the Y-axis direction and contacts the first and second fins.

Potential applications of this technology:
* Data multiplexing in electronic devices and systems.
* Signal routing and selection in integrated circuits.
* Communication systems requiring efficient data transmission.

Problems solved by this technology:
* Efficiently selecting and routing specific data signals.
* Minimizing signal interference and crosstalk.
* Streamlining data transmission processes.

Benefits of this technology:
* Improved data processing and transmission efficiency.
* Enhanced signal integrity and reliability.
* Compact and space-saving design for integrated circuits.


==Original Abstract Submitted==

A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.



[[Category:G06F30/392]]
[[Category:G06F30/347]]
[[Category:G06F30/39]]
[[Category:H01L27/02]]