View source for 18303647. TEST STRUCTURES TO DETERMINE INTEGRATED CIRCUIT BONDING ENERGIES AND METHODS OF MAKING AND USING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)

=TEST STRUCTURES TO DETERMINE INTEGRATED CIRCUIT BONDING ENERGIES AND METHODS OF MAKING AND USING THE SAME=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Company Limited|Taiwan Semiconductor Manufacturing Company Limited]]


[[Category:Taiwan Semiconductor Manufacturing Company Limited]]

==Inventor(s)==

[[:Category:Yu-Sheng Lin of Zhubei (TW)|Yu-Sheng Lin of Zhubei (TW)]][[Category:Yu-Sheng Lin of Zhubei (TW)]]

[[:Category:Jyun-Lin Wu of Hsinchu City (TW)|Jyun-Lin Wu of Hsinchu City (TW)]][[Category:Jyun-Lin Wu of Hsinchu City (TW)]]

[[:Category:Yao-Chun Chuang of Hsinchu City (TW)|Yao-Chun Chuang of Hsinchu City (TW)]][[Category:Yao-Chun Chuang of Hsinchu City (TW)]]

[[:Category:Chin-Fu Kao of Taipei City (TW)|Chin-Fu Kao of Taipei City (TW)]][[Category:Chin-Fu Kao of Taipei City (TW)]]

==TEST STRUCTURES TO DETERMINE INTEGRATED CIRCUIT BONDING ENERGIES AND METHODS OF MAKING AND USING THE SAME - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18303647 titled 'TEST STRUCTURES TO DETERMINE INTEGRATED CIRCUIT BONDING ENERGIES AND METHODS OF MAKING AND USING THE SAME

==Simplified Explanation==

The embodiment interfacial bonding test structure described in the abstract consists of a sandwich structure formed by bonding two semiconductor dies between two substrates using adhesive. The structure allows for displacement of the semiconductor dies along a direction parallel to the planar surfaces of the substrates.

* The test structure includes a first substrate with a planar surface, a second substrate with a parallel planar surface, and two semiconductor dies bonded between them.
* The semiconductor dies are bonded to the substrates using different adhesives.
* The structure allows for displacement of the semiconductor dies along a direction parallel to the planar surfaces.
* The second substrate features a notch that overlaps with the separation between the semiconductor dies.

== Potential Applications ==
This technology could be used in the testing and evaluation of interfacial bonding strength in semiconductor devices.

== Problems Solved ==
This technology helps in assessing the quality and reliability of interfacial bonding in semiconductor devices.

== Benefits ==
The test structure provides a controlled environment for studying interfacial bonding, leading to improved understanding and optimization of bonding processes.

== Potential Commercial Applications ==
One potential commercial application of this technology could be in the semiconductor manufacturing industry for quality control and process optimization.

== Possible Prior Art ==
Prior art in the field of semiconductor testing and evaluation may include similar test structures used for assessing bonding strength in semiconductor devices.

=== Unanswered Questions ===

=== How does this technology compare to existing methods for testing interfacial bonding strength in semiconductor devices? ===
This technology offers a controlled and precise method for evaluating interfacial bonding strength, but it would be beneficial to compare its effectiveness and efficiency with other testing methods currently in use.

=== What are the limitations of this test structure in terms of scalability and applicability to different types of semiconductor devices? ===
It would be important to understand the scalability of this test structure and its suitability for various semiconductor devices with different sizes and configurations.


==Original Abstract Submitted==

An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.



[[Category:G01N3/20]]