View source for 18243442. RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR PREVENTING START-UP FAILURE, AND IQ DIVIDER CIRCUIT simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR PREVENTING START-UP FAILURE, AND IQ DIVIDER CIRCUIT=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Juyun Lee of Suwon-si (KR)|Juyun Lee of Suwon-si (KR)]][[Category:Juyun Lee of Suwon-si (KR)]]

[[:Category:Vishnu Kalyanamahadevi Gopalan Jawarlal of Bangalore (IN)|Vishnu Kalyanamahadevi Gopalan Jawarlal of Bangalore (IN)]][[Category:Vishnu Kalyanamahadevi Gopalan Jawarlal of Bangalore (IN)]]

[[:Category:Kang Jik Kim of Suwon-si (KR)|Kang Jik Kim of Suwon-si (KR)]][[Category:Kang Jik Kim of Suwon-si (KR)]]

[[:Category:Hyo Gyuem Rhew of Suwon-si (KR)|Hyo Gyuem Rhew of Suwon-si (KR)]][[Category:Hyo Gyuem Rhew of Suwon-si (KR)]]

[[:Category:Jae Hyun Park of Suwon-si (KR)|Jae Hyun Park of Suwon-si (KR)]][[Category:Jae Hyun Park of Suwon-si (KR)]]

==RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR PREVENTING START-UP FAILURE, AND IQ DIVIDER CIRCUIT - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18243442 titled 'RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR PREVENTING START-UP FAILURE, AND IQ DIVIDER CIRCUIT

==Simplified Explanation==

The abstract describes a clock frequency divider circuit and a receiver. Here is a simplified explanation of the abstract:

* The clock frequency divider circuit includes a reset retimer circuit that receives a reset signal and a clock signal. It outputs a reset buffer signal, which is a buffered version of the reset signal, and a reset synchronization signal, which is the reset signal synchronized with the clock signal.
* The circuit also includes a clock buffer circuit that receives the clock signal and the reset synchronization signal. It outputs a clock buffer signal, which is a buffered version of the clock signal.
* Additionally, an IQ divider circuit is included in the circuit. It uses the reset buffer signal and the clock buffer signal to generate four output signals with different phases.

Potential applications of this technology:

* Clock frequency division in electronic devices.
* Synchronization of reset signals with clock signals.
* Generation of multiple output signals with different phases.

Problems solved by this technology:

* Efficient clock frequency division.
* Accurate synchronization of reset signals with clock signals.
* Generation of multiple output signals with precise phase differences.

Benefits of this technology:

* Improved performance and efficiency in electronic devices.
* Enhanced synchronization and timing accuracy.
* Flexibility in generating multiple output signals with different phases.


==Original Abstract Submitted==

A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.



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