View source for 18231514. BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS simplified abstract (Micron Technology, Inc.)

=BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Guang Hu of Mountain View CA (US)|Guang Hu of Mountain View CA (US)]][[Category:Guang Hu of Mountain View CA (US)]]

[[:Category:Nicola Ciocchini of Boise ID (US)|Nicola Ciocchini of Boise ID (US)]][[Category:Nicola Ciocchini of Boise ID (US)]]

==BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18231514 titled 'BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS

==Simplified Explanation==

The memory device described in the patent application includes a memory array and control logic that organizes memory arrays into bins based on elapsed time since programming, with each bin assigned a read level offset to meet error correction decoder specifications. When a read operation is requested, the operation is performed based on the set of bins.

* Memory device includes memory array and control logic
* Bins are defined based on elapsed time since programming
* Each bin has a read level offset for error correction decoder specifications
* Read operations are performed based on the set of bins

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### Potential Applications
* Data storage devices
* Solid-state drives
* Embedded systems

### Problems Solved
* Maintaining data integrity in memory arrays
* Meeting error correction decoder throughput specifications

### Benefits
* Improved data reliability
* Enhanced error correction capabilities
* Optimal performance based on elapsed time since programming


==Original Abstract Submitted==

A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.



[[Category:G11C29/32]]