View source for 18223249. COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY simplified abstract (Micron Technology, Inc.)

=COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Matthew A. Prather of Boise ID (US)|Matthew A. Prather of Boise ID (US)]][[Category:Matthew A. Prather of Boise ID (US)]]

==COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18223249 titled 'COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY

==Simplified Explanation==

The apparatus described in the patent application consists of a single integrated circuit (IC) that is connected to a host device via a host bus and to multiple memories via a memory bus. The IC includes a logic buffer module for buffering data, command, address, and clock signals between the host device and memories, as well as a power management integrated circuit (PMIC) module for regulating voltage and monitoring current supplied to the memories.

* The apparatus comprises a single IC that connects to a host device and multiple memories.
* The IC includes a logic buffer module for buffering various signals between the host device and memories.
* The IC also includes a PMIC module for regulating voltage and monitoring current to the memories.

---

### Potential Applications
* Data storage devices
* Computer systems
* Networking equipment

### Problems Solved
* Efficient data transfer between host devices and memories
* Proper regulation of voltage and monitoring of current for memories

### Benefits
* Improved data transfer speeds
* Enhanced power management for memories
* Simplified design and integration of memory systems


==Original Abstract Submitted==

An apparatus, comprising a plurality of memories and a single integrated circuit (IC) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories, and a power management integrated circuit (PMIC) module that is configured to regulate voltage and monitor current provided to the plurality of memories.



[[Category:G06F3/06]]