View source for 18176347. FLASH MEMORY DEVICE FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SENSING METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=FLASH MEMORY DEVICE FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SENSING METHOD THEREOF=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Tae-Hong Kwon of Suwon-si (KR)|Tae-Hong Kwon of Suwon-si (KR)]][[Category:Tae-Hong Kwon of Suwon-si (KR)]]

[[:Category:Kiwhan Song of Suwon-si (KR)|Kiwhan Song of Suwon-si (KR)]][[Category:Kiwhan Song of Suwon-si (KR)]]

[[:Category:Gyosoo Choo of Suwon-si (KR)|Gyosoo Choo of Suwon-si (KR)]][[Category:Gyosoo Choo of Suwon-si (KR)]]

==FLASH MEMORY DEVICE FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SENSING METHOD THEREOF - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18176347 titled 'FLASH MEMORY DEVICE FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SENSING METHOD THEREOF

==Simplified Explanation==

The abstract describes a flash memory device that includes a cell string with multiple memory cells, a page buffer connected to the cell string and a bit line, and a voltage regulator that provides a source voltage to the page buffer. The page buffer is designed to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line. The page buffer includes a latch with first and second inverters connected between a latch node and an inverted latch node, and a pull-down NMOS transistor that transfers the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by supplying the source voltage to the pull-down NMOS transistor.

* The flash memory device reduces the variation range of the trip voltage by utilizing the characteristics of the pull-down NMOS transistor.
* The device allows for sufficient security of the OFF cell margin and ON cell margin by adjusting the trip voltage level using the source voltage.
* The use of a latch and a pull-down NMOS transistor in the page buffer enables efficient sensing of data stored in the memory cells.

Potential applications of this technology:
* Flash memory devices are commonly used in various electronic devices such as smartphones, tablets, and solid-state drives (SSDs).
* The improved trip voltage control and sensing capabilities of this flash memory device can enhance the performance and reliability of these electronic devices.

Problems solved by this technology:
* Flash memory devices often face challenges in accurately sensing data stored in memory cells due to variations in trip voltage.
* The use of only the pull-down NMOS transistor in adjusting the trip voltage helps reduce the variation range, improving the accuracy of data sensing.

Benefits of this technology:
* The flash memory device provides a more reliable and efficient method for sensing data stored in memory cells.
* By adjusting the trip voltage level, the device ensures sufficient security of the OFF cell margin and ON cell margin, improving overall performance and reliability.
* The reduced trip voltage variation range helps minimize errors in data sensing, leading to improved data integrity.


==Original Abstract Submitted==

Various example embodiments provide a flash memory device, comprising a cell string having a plurality of memory cells; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell from among the plurality of memory cells by precharging a sensing node connected to the bit line; and a voltage regulator providing a source voltage to the page buffer. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for ping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device according to the embodiment of the present invention may reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, according to the present invention, an OFF cell margin and an ON cell margin may be sufficiently secured by adjusting the level of the trip voltage Vtrip using the source voltage Vs.



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