View source for 18116019. TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPLE MEMORY DEVICES simplified abstract (SK hynix Inc.)

=TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPLE MEMORY DEVICES=


==Organization Name==

[[:Category:SK hynix Inc.|SK hynix Inc.]]


[[Category:SK hynix Inc.]]

==Inventor(s)==

[[:Category:Sang Ah Hyun of Icheon-si Gyeonggi-do (KR)|Sang Ah Hyun of Icheon-si Gyeonggi-do (KR)]][[Category:Sang Ah Hyun of Icheon-si Gyeonggi-do (KR)]]

[[:Category:Yong Ho Seo of Icheon-si Gyeonggi-do (KR)|Yong Ho Seo of Icheon-si Gyeonggi-do (KR)]][[Category:Yong Ho Seo of Icheon-si Gyeonggi-do (KR)]]

[[:Category:Woo Sik Jung of Icheon-si Gyeonggi-do (KR)|Woo Sik Jung of Icheon-si Gyeonggi-do (KR)]][[Category:Woo Sik Jung of Icheon-si Gyeonggi-do (KR)]]

[[:Category:Jun Phyo Lee of Icheon-si Gyeonggi-do (KR)|Jun Phyo Lee of Icheon-si Gyeonggi-do (KR)]][[Category:Jun Phyo Lee of Icheon-si Gyeonggi-do (KR)]]

[[:Category:Bong Hwa Jeong of Icheon-si Gyeonggi-do (KR)|Bong Hwa Jeong of Icheon-si Gyeonggi-do (KR)]][[Category:Bong Hwa Jeong of Icheon-si Gyeonggi-do (KR)]]

==TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPLE MEMORY DEVICES - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18116019 titled 'TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPLE MEMORY DEVICES

==Simplified Explanation==

The test system described in the abstract includes a test device, a test dock, and a memory device. The test device outputs a command address and receives a comparison signal from the test dock. The memory device enters the test mode based on the command address, sets an initial value, performs a calculation operation, generates a row address and a command address during a pre-charge operation, and outputs internal data as the comparison signal to the test device.

* Test system components:
    - Test device
    - Test dock
    - Memory device

* Functions of the memory device:
    - Enters test mode based on command address
    - Sets initial value
    - Performs calculation operation
    - Generates row address and command address
    - Outputs internal data as comparison signal

* Operation during pre-charge:
    - Logic level combination of command address
    - Generation of row address and command address

* Output to test device:
    - Internal data as comparison signal

== Potential Applications ==
This technology could be used in:
- Semiconductor testing
- Memory testing
- Circuit board testing

== Problems Solved ==
This technology helps in:
- Efficient testing of memory devices
- Streamlining test processes
- Improving accuracy of test results

== Benefits ==
The benefits of this technology include:
- Faster testing procedures
- Enhanced reliability of test data
- Cost-effective testing solutions

== Potential Commercial Applications ==
The potential commercial applications of this technology can be seen in:
- Electronics manufacturing industry
- Semiconductor industry
- Testing equipment suppliers

== Possible Prior Art ==
One possible prior art could be:
- Memory testing systems with similar functionalities

=== Unanswered Questions ===

=== How does this technology compare to existing memory testing systems? ===
This article does not provide a direct comparison with existing memory testing systems. It would be helpful to understand the specific advantages and differences this technology offers.

=== What are the specific technical specifications of the test device and memory device in this system? ===
The article does not delve into the technical specifications of the test device and memory device. Understanding the detailed specifications could provide insights into the performance and capabilities of this technology.


==Original Abstract Submitted==

A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.



[[Category:G11C29/38]]
[[Category:G11C29/12]]
[[Category:G11C29/18]]