View source for 18101123. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM PERFORMING ERROR CORRECTION OPERATION simplified abstract (SK hynix Inc.)

=SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM PERFORMING ERROR CORRECTION OPERATION=


==Organization Name==

[[:Category:SK hynix Inc.|SK hynix Inc.]]


[[Category:SK hynix Inc.]]

==Inventor(s)==

[[:Category:Hong Ki Moon of Gyeonggi-do (KR)|Hong Ki Moon of Gyeonggi-do (KR)]][[Category:Hong Ki Moon of Gyeonggi-do (KR)]]

==SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM PERFORMING ERROR CORRECTION OPERATION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18101123 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM PERFORMING ERROR CORRECTION OPERATION

==Simplified Explanation==

The semiconductor memory device described in the patent application is designed to perform error correction operations on data stored in the memory. Here is a simplified explanation of the innovation:

* Command address control circuit generates error correction commands and selection addresses based on external control signals.
* Error flag generation circuit corrects errors in data and generates error flags based on error patterns.
* Error information processing circuit generates target addresses for error correction operations based on error flags.

== Potential Applications ==
The technology can be applied in various industries such as:
* Data storage
* Communication systems
* Information technology

== Problems Solved ==
The technology addresses the following issues:
* Data corruption
* Error detection and correction
* Data integrity

== Benefits ==
The benefits of this technology include:
* Improved data reliability
* Enhanced error correction capabilities
* Increased data integrity

== Potential Commercial Applications ==
The technology can be utilized in:
* Memory modules
* Data centers
* Networking equipment

== Possible Prior Art ==
One possible prior art for this technology could be:
* Error correction codes in memory devices

== Unanswered Questions ==
1. How does the error flag generation circuit determine the error patterns in the data?
2. What specific types of errors can be corrected using this technology?


==Original Abstract Submitted==

A semiconductor memory device includes a command address control circuit configured to generate an error correction command and selection address for executing an error correction operation by receiving an external control signal, an error flag generation circuit configured to correct an error of data corresponding to the selection address and configured to generate a target error flag based on a pattern of the error of the data, and an error information processing circuit configured to generate a target address that is used as the selection address based on the target error flag in a target error correction operation that is executed based on the error correction operation.



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