View source for 18099014. METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING ONE MEMORY TO MEMORY TRANSFER OPERATION simplified abstract (SambaNova Systems, Inc.)

=METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING ONE MEMORY TO MEMORY TRANSFER OPERATION=


==Organization Name==

[[:Category:SambaNova Systems, Inc.|SambaNova Systems, Inc.]]


[[Category:SambaNova Systems, Inc.]]

==Inventor(s)==

[[:Category:Arnav Goel of Palo Alto CA (US)|Arnav Goel of Palo Alto CA (US)]][[Category:Arnav Goel of Palo Alto CA (US)]]

[[:Category:Neal Sanghvi of Palo Alto CA (US)|Neal Sanghvi of Palo Alto CA (US)]][[Category:Neal Sanghvi of Palo Alto CA (US)]]

[[:Category:Jiayu Bai of Palo Alto CA (US)|Jiayu Bai of Palo Alto CA (US)]][[Category:Jiayu Bai of Palo Alto CA (US)]]

[[:Category:Qi Zheng of Palo Alto CA (US)|Qi Zheng of Palo Alto CA (US)]][[Category:Qi Zheng of Palo Alto CA (US)]]

[[:Category:Ravinder Kumar of Palo Alto CA (US)|Ravinder Kumar of Palo Alto CA (US)]][[Category:Ravinder Kumar of Palo Alto CA (US)]]

==METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING ONE MEMORY TO MEMORY TRANSFER OPERATION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18099014 titled 'METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING ONE MEMORY TO MEMORY TRANSFER OPERATION

'''Simplified Explanation''': 

The patent application describes a system with multiple processors and memories that can transfer data between them efficiently.

'''Key Features and Innovation''':
* Heterogeneous processing system with host processor, first processor, and second processor.
* Data transfer resource for memory to memory transfer operations.
* Mapping of virtual addresses to physical addresses for efficient data transfer.
* Configuration of processors for optimized memory operations.

'''Potential Applications''':
This technology can be used in:
* High-performance computing systems.
* Data centers for efficient data processing.
* Embedded systems for optimized memory operations.

'''Problems Solved''':
* Improving data transfer efficiency between memories.
* Enhancing overall system performance.
* Streamlining memory to memory operations.

'''Benefits''':
* Faster data transfer speeds.
* Enhanced system performance.
* Optimized memory operations.

'''Commercial Applications''':
Title: Enhanced Data Transfer System for High-Performance Computing
This technology can be utilized in:
* Supercomputers for complex calculations.
* Cloud computing for rapid data processing.
* IoT devices for efficient memory operations.

'''Prior Art''':
Readers can explore prior patents related to heterogeneous processing systems and memory optimization techniques.

'''Frequently Updated Research''':
Stay updated on the latest advancements in heterogeneous processing systems and memory optimization technologies.

'''Questions about Heterogeneous Processing Systems''':
1. How does this technology improve data transfer efficiency between memories?
2. What are the potential commercial applications of this system?


==Original Abstract Submitted==

A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.



[[Category:G06F13/28]]
[[Category:G06F12/02]]
[[Category:G06F13/16]]
[[Category:CPC_G06F13/28]]