View source for 18099006. METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING TWO MEMORY TO MEMORY TRANSFER OPERATIONS simplified abstract (SambaNova Systems, Inc.)

=METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING TWO MEMORY TO MEMORY TRANSFER OPERATIONS=


==Organization Name==

[[:Category:SambaNova Systems, Inc.|SambaNova Systems, Inc.]]


[[Category:SambaNova Systems, Inc.]]

==Inventor(s)==

[[:Category:Arnav Goel of Palo Alto CA (US)|Arnav Goel of Palo Alto CA (US)]][[Category:Arnav Goel of Palo Alto CA (US)]]

[[:Category:Neal Sanghvi of Palo Alto CA (US)|Neal Sanghvi of Palo Alto CA (US)]][[Category:Neal Sanghvi of Palo Alto CA (US)]]

[[:Category:Jiayu Bai of Palo Alto CA (US)|Jiayu Bai of Palo Alto CA (US)]][[Category:Jiayu Bai of Palo Alto CA (US)]]

[[:Category:Qi Zheng of Palo Alto CA (US)|Qi Zheng of Palo Alto CA (US)]][[Category:Qi Zheng of Palo Alto CA (US)]]

[[:Category:Ravinder Kumar of Palo Alto CA (US)|Ravinder Kumar of Palo Alto CA (US)]][[Category:Ravinder Kumar of Palo Alto CA (US)]]

==METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING TWO MEMORY TO MEMORY TRANSFER OPERATIONS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18099006 titled 'METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING TWO MEMORY TO MEMORY TRANSFER OPERATIONS

'''Simplified Explanation''': 

This patent application describes a heterogeneous processing system that includes a host processor, first and second processors, and multiple data transfer resources. The system is designed to efficiently transfer data between the processors using buffer space in the host memory.

* The system includes a host processor with allocated buffer space in the host memory.
* First processor executes a part of an application and transfers data to the buffer space.
* Data transfer resources are programmed to move data between the processors and memory.
* Second processor executes another part of the application and generates data stored in its memory.
* Data transfer resources may include a DMA engine for efficient data transfer.

'''Key Features and Innovation''':

* Heterogeneous processing system with multiple processors and data transfer resources.
* Efficient data transfer using buffer space and DMA engine.
* Allocation of buffer space in host memory for seamless data movement.
* Reconfigurable processors or compute engines for versatile processing capabilities.

'''Potential Applications''':

* High-performance computing tasks.
* Data-intensive applications requiring fast data transfer.
* Real-time processing and data analysis.

'''Problems Solved''':

* Slow data transfer between processors.
* Inefficient use of memory resources.
* Lack of flexibility in processing tasks.

'''Benefits''':

* Improved data transfer speeds.
* Enhanced processing capabilities.
* Efficient use of memory resources.

'''Commercial Applications''''':

* Cloud computing services.
* Data centers.
* Scientific research and simulations.

'''Prior Art''''':

Prior art related to this technology may include research on heterogeneous processing systems, data transfer methods, and reconfigurable processors.

'''Frequently Updated Research''''':

Researchers may be exploring new algorithms for optimizing data transfer in heterogeneous processing systems, advancements in reconfigurable processor technology, and applications of DMA engines in high-performance computing.

'''Questions about Heterogeneous Processing Systems''':

1. How does the use of buffer space improve data transfer efficiency in heterogeneous processing systems?
2. What are the potential limitations of using reconfigurable processors in this type of system?


==Original Abstract Submitted==

A heterogeneous processing system and method including a host processor with a host memory having allocated buffer space, first and second processors each with memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the processors and the transfer resources. The first processor executes a first part of an application generating first data stored into the first memory. A data transfer resource is programed to transfer the first data to the buffer space and to transfer the first data from the buffer space into the second memory. The second processor executes a second part of the application generating second data stored into the second memory. The data transfer resources may include a DMA engine in which the buffer space is DMA addressable. One of the first and second processors may be a reconfigurable processor, a compute engine, or a reconfigurable dataflow unit.



[[Category:G06F13/16]]
[[Category:G06F9/50]]
[[Category:G06F13/28]]
[[Category:CPC_G06F13/1673]]