View source for 18093728. RANDOM DATA GENERATION CIRCUIT AND READ/WRITE TRAINING CIRCUIT simplified abstract (Changxin Memory Technologies, Inc.)

=RANDOM DATA GENERATION CIRCUIT AND READ/WRITE TRAINING CIRCUIT=


==Organization Name==

[[:Category:Changxin Memory Technologies, Inc.|Changxin Memory Technologies, Inc.]]


[[Category:Changxin Memory Technologies, Inc.]]

==Inventor(s)==

[[:Category:Biao Cheng of HEFEI (CN)|Biao Cheng of HEFEI (CN)]][[Category:Biao Cheng of HEFEI (CN)]]

[[:Category:Tianchen Lu of HEFEI (CN)|Tianchen Lu of HEFEI (CN)]][[Category:Tianchen Lu of HEFEI (CN)]]

==RANDOM DATA GENERATION CIRCUIT AND READ/WRITE TRAINING CIRCUIT - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18093728 titled 'RANDOM DATA GENERATION CIRCUIT AND READ/WRITE TRAINING CIRCUIT

==Simplified Explanation==

The abstract describes a random data generation circuit that includes two shift registers and a parallel-to-serial circuit. The first shift register has n output ends, while the second shift register has n output ends. Each output end of both shift registers outputs 1-bit data in a clock cycle. The parallel-to-serial circuit is connected to the output ends of the first shift register and converts the parallel data into serial data for output. The initial values of the two shift registers are different.

* The circuit uses two shift registers to generate data in parallel.
* The parallel data generated by the shift registers is converted into serial data for output.
* The initial values of the two shift registers are different.

==Potential Applications==
* Random number generation
* Data encryption
* Data scrambling

==Problems Solved==
* Efficient generation of random data in parallel
* Conversion of parallel data to serial data for output

==Benefits==
* Faster data generation compared to traditional methods
* Improved data security through randomization
* Versatile application in various fields requiring random data


==Original Abstract Submitted==

A random data generation circuit includes: a first shift register and a second shift register. The first shift register includes n output ends Q to Qn, the second shift register includes n output ends Qn+1 to Q, and each of the output ends outputs 1-bit data in a clock cycle of a clock signal; and a parallel-to-serial circuit, coupled to the output ends Q to Qand configured to convert parallel data output from Q to Qin a clock cycle into serial data for output. An initial value of the first shift register is different from an initial value of the second shift register. Data may be generated in parallel by using two shift registers, and the parallel data generated by the two shift registers is converted into serial data by using the parallel-to-serial circuit to be output.



[[Category:G11C7/10]]
[[Category:G11C7/22]]
[[Category:H03K19/21]]