View source for 17988186. DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE simplified abstract (QUALCOMM Incorporated)

=DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE=


==Organization Name==

[[:Category:QUALCOMM Incorporated|QUALCOMM Incorporated]]


[[Category:QUALCOMM Incorporated]]

==Inventor(s)==

[[:Category:Yong Xu of San Diego CA (US)|Yong Xu of San Diego CA (US)]][[Category:Yong Xu of San Diego CA (US)]]

[[:Category:Boris Dimitrov Andreev of San Diego CA (US)|Boris Dimitrov Andreev of San Diego CA (US)]][[Category:Boris Dimitrov Andreev of San Diego CA (US)]]

[[:Category:Yuxin Li of San Diego CA (US)|Yuxin Li of San Diego CA (US)]][[Category:Yuxin Li of San Diego CA (US)]]

[[:Category:Vikas Mahendiyan of San Diego CA (US)|Vikas Mahendiyan of San Diego CA (US)]][[Category:Vikas Mahendiyan of San Diego CA (US)]]

==DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17988186 titled 'DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE

==Simplified Explanation==

The abstract describes a system with two clock sources, an OR gate, clock paths, and clock gating circuits.

* The system includes a first clock source generating a first clock signal.
* A second clock source generates a second clock signal.
* An OR gate with two inputs and an output is connected to the clock path.
* A first clock gating circuit is connected between the first clock source and the first input of the OR gate.
* A second clock gating circuit is connected between the second clock source and the second input of the OR gate.

== Potential Applications ==
This technology could be applied in:
* Synchronization systems
* Data processing systems
* Communication networks

== Problems Solved ==
This technology helps in:
* Improving clock signal reliability
* Reducing clock signal interference
* Enhancing system performance

== Benefits ==
The benefits of this technology include:
* Enhanced system stability
* Increased data processing speed
* Improved overall system efficiency

== Potential Commercial Applications ==
Potential commercial applications of this technology could be in:
* Telecommunications equipment
* Computer hardware
* Industrial automation systems

== Possible Prior Art ==
One possible prior art for this technology could be:
* Clock signal synchronization systems used in telecommunications networks.

== Unanswered Questions ==

=== How does this technology impact power consumption in the system? ===
This article does not provide information on the power consumption implications of implementing this technology.

=== Are there any limitations to the number of clock sources that can be integrated into this system? ===
The article does not address any limitations on the number of clock sources that can be accommodated by this system.


==Original Abstract Submitted==

In certain aspects, a system includes a first clock source configured to generate a first clock signal, a second clock source configured to generate a second clock signal, a clock path, and an OR gate having a first input, a second input, and an output, wherein the output of the OR gate is coupled to the clock path. The system also includes a first clock gating circuit coupled between the first clock source and the first input of the OR gate, and a second clock gating circuit coupled between the second clock source and the second input of the OR gate.



[[Category:G11C11/4076]]
[[Category:H03K19/20]]
[[Category:H03L7/081]]