View source for 17963970. REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP simplified abstract (QUALCOMM Incorporated)

=REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP=


==Organization Name==

[[:Category:QUALCOMM Incorporated|QUALCOMM Incorporated]]


[[Category:QUALCOMM Incorporated]]

==Inventor(s)==

[[:Category:Jianwen Ye of Apex NC (US)|Jianwen Ye of Apex NC (US)]][[Category:Jianwen Ye of Apex NC (US)]]

[[:Category:Julian Puscar of Cary NC (US)|Julian Puscar of Cary NC (US)]][[Category:Julian Puscar of Cary NC (US)]]

==REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17963970 titled 'REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP

==Simplified Explanation==

The patent application describes a data communication interface with a delay-locked loop, phase interpolator, clock and data recovery circuit, and calibration circuit.

* The delay-locked loop generates a receive clock signal based on timing information from a clock channel.
* The phase interpolator provides a phase-shifted clock signal based on transitions in a data signal received over a data channel.
* The clock and data recovery circuit captures data using the phase-shifted clock signal.
* The calibration circuit calibrates the delay-locked loop and the clock and data recovery circuit.

== Potential Applications ==
This technology could be applied in high-speed data communication systems, such as in networking equipment, telecommunications devices, and data centers.

== Problems Solved ==
1. Synchronization: Ensures accurate timing and synchronization between data signals and clock signals.
2. Calibration: Allows for precise calibration of the delay-locked loop and the clock and data recovery circuit, improving overall system performance.

== Benefits ==
1. Improved Data Integrity: Ensures reliable data transmission by maintaining accurate timing relationships.
2. Enhanced Performance: Optimizes the operation of the data communication interface for efficient data transfer.

== Potential Commercial Applications ==
Optimized Data Communication Interface for High-Speed Networks

== Possible Prior Art ==
Prior art may include similar patents related to delay-locked loops, phase interpolators, clock and data recovery circuits, and calibration circuits in data communication systems.

=== Unanswered Questions ===

=== How does this technology compare to existing solutions in terms of performance and cost? ===
This article does not provide a direct comparison with existing solutions in terms of performance and cost. Further research and analysis would be needed to determine the competitive advantages of this technology.

=== What are the specific technical specifications required for implementing this technology in different types of data communication systems? ===
The article does not delve into the specific technical specifications required for implementing this technology in various data communication systems. Additional information would be necessary to understand the compatibility and integration aspects of this innovation.


==Original Abstract Submitted==

A data communication interface has a delay-locked loop configured to generate a receive clock signal based on timing information provided by a signal received over a clock channel of a data communication link, a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the receive clock signal based on timing of transitions in a data signal received over a data channel of the data communication link, a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal, and a calibration circuit. The calibration circuit is configured to calibrate the delay-locked loop while the clock and data recovery circuit is in an idle state, recalibrate the delay-locked loop when the clock and data recovery circuit is activated, and calibrate the clock and data recovery circuit after recalibrating the delay-locked loop.



[[Category:H04L7/033]]
[[Category:H03L7/08]]
[[Category:H03L7/081]]
[[Category:H04L7/00]]