View source for 17946925. VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY simplified abstract (Micron Technology, Inc.)

=VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Scott E. Sills of Boise ID (US)|Scott E. Sills of Boise ID (US)]][[Category:Scott E. Sills of Boise ID (US)]]

[[:Category:Si-Woo Lee of Boise ID (US)|Si-Woo Lee of Boise ID (US)]][[Category:Si-Woo Lee of Boise ID (US)]]

[[:Category:David K. Hwang of Boise ID (US)|David K. Hwang of Boise ID (US)]][[Category:David K. Hwang of Boise ID (US)]]

[[:Category:Yoshitaka Nakamura of Boise ID (US)|Yoshitaka Nakamura of Boise ID (US)]][[Category:Yoshitaka Nakamura of Boise ID (US)]]

[[:Category:Yuanzhi Ma of Boise ID (US)|Yuanzhi Ma of Boise ID (US)]][[Category:Yuanzhi Ma of Boise ID (US)]]

[[:Category:Glen H. Walters of Boise ID (US)|Glen H. Walters of Boise ID (US)]][[Category:Glen H. Walters of Boise ID (US)]]

==VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17946925 titled 'VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY

==Simplified Explanation==

The patent application describes a system for vertically stacked memory cells with horizontally oriented access devices and storage nodes. The access devices have first and second source/drain regions separated by silicon channel regions, with a digit line formed in a trench adjacent to the first source/drain regions.

* Horizontally stacked memory cells with access devices and storage nodes
* Access devices with first and second source/drain regions separated by silicon channel regions
* Digit line formed in a trench adjacent to the first source/drain regions
* Electrically isolated digit lines in trenches
* Shared digit lines between horizontal access devices in separate arrays
* Storage nodes coupled to the second source/drain regions
* Vertical digit lines coupled to the first source/drain regions

== Potential Applications ==
This technology could be applied in:
* High-density memory modules
* Data storage devices
* Embedded systems

== Problems Solved ==
This technology addresses:
* Increasing memory storage capacity
* Improving data access speed
* Enhancing memory cell reliability

== Benefits ==
The benefits of this technology include:
* Higher memory density
* Faster data access
* Improved overall system performance

== Potential Commercial Applications ==
Potential commercial applications of this technology include:
* Memory chip manufacturing
* Data center storage solutions
* Consumer electronics devices

== Possible Prior Art ==
One possible prior art for this technology could be:
* Stacked memory cells with vertical access devices and storage nodes

== Unanswered Questions ==
=== How does this technology impact power consumption in memory systems? ===
The patent application does not provide specific details on the power consumption implications of this technology.

=== What are the potential limitations of vertically stacked memory cells with horizontally oriented access devices? ===
The patent application does not discuss any potential limitations or challenges that may arise from implementing this technology.


==Original Abstract Submitted==

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.



[[Category:H01L27/108]]