View source for 17894554. MEMORY DEVICE INCLUDING MERGED WRITE DRIVER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=MEMORY DEVICE INCLUDING MERGED WRITE DRIVER=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Gyuseong Kang of Goyang-si (KR)|Gyuseong Kang of Goyang-si (KR)]][[Category:Gyuseong Kang of Goyang-si (KR)]]

[[:Category:Hyuntaek Jung of Seoul (KR)|Hyuntaek Jung of Seoul (KR)]][[Category:Hyuntaek Jung of Seoul (KR)]]

==MEMORY DEVICE INCLUDING MERGED WRITE DRIVER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17894554 titled 'MEMORY DEVICE INCLUDING MERGED WRITE DRIVER

==Simplified Explanation==

The abstract describes a memory device that includes a memory cell array with two sub memory cell arrays, a merged write driver, and a column decoder. The merged write driver receives n-bit data and outputs different write voltages to a merged node based on the data bits. The column decoder applies the corresponding voltages from the merged node to each memory cell.

* The memory device has a memory cell array with two sub memory cell arrays.
* The merged write driver receives n-bit data and outputs different write voltages to a merged node.
* The column decoder applies the corresponding voltages from the merged node to each memory cell.

Potential applications of this technology:
* Memory devices in computers, smartphones, and other electronic devices.
* Data storage systems in cloud computing and data centers.

Problems solved by this technology:
* Efficient writing of data to memory cells.
* Simplified circuit design for memory devices.

Benefits of this technology:
* Improved performance and reliability of memory devices.
* Reduced power consumption and cost.
* Increased data storage capacity.


==Original Abstract Submitted==

A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.



[[Category:G11C11/16]]
[[Category:G11C8/10]]