View source for 17885520. SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Tong Zhang of Mountain View CA (US)|Tong Zhang of Mountain View CA (US)]][[Category:Tong Zhang of Mountain View CA (US)]]

[[:Category:Heekwon Park of San Jose CA (US)|Heekwon Park of San Jose CA (US)]][[Category:Heekwon Park of San Jose CA (US)]]

[[:Category:Rekha Pitchumani of Oak Hill VA (US)|Rekha Pitchumani of Oak Hill VA (US)]][[Category:Rekha Pitchumani of Oak Hill VA (US)]]

[[:Category:Yang Seok Ki of Palo Alto CA (US)|Yang Seok Ki of Palo Alto CA (US)]][[Category:Yang Seok Ki of Palo Alto CA (US)]]

==SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17885520 titled 'SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES

==Simplified Explanation==

The abstract describes a system that includes a processor, a first storage device, and a second storage device. The first and second storage devices are part of a redundant array of independent disks (RAID) and support a cache coherent interconnect protocol. The system also includes a decoder associated with the second storage device.

* The system includes a processor that can issue byte level protocol requests with byte addresses.
* The first and second storage devices are part of a RAID and support a cache coherent interconnect protocol.
* The first storage device has a first address range, and the second storage device has a second address range.
* The second storage device provides a RAID address range associated with the first and second address ranges.
* The decoder in the second storage device receives requests from the processor and determines if the byte address in the RAID address range is associated with a target address range.

== Potential Applications ==
* Data storage systems
* RAID systems
* Cache coherent interconnect protocols

== Problems Solved ==
* Efficient management of byte level protocol requests in a RAID system
* Ensuring cache coherence in a storage system

== Benefits ==
* Improved performance and efficiency in handling byte level protocol requests
* Enhanced cache coherence in a storage system


==Original Abstract Submitted==

A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.



[[Category:G06F3/06]]