View source for 17884755. CONCURRENT COMPUTE CONTEXT simplified abstract (Intel Corporation)

=CONCURRENT COMPUTE CONTEXT=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Joydeep Ray of Folsom CA (US)|Joydeep Ray of Folsom CA (US)]][[Category:Joydeep Ray of Folsom CA (US)]]

[[:Category:Vasanth Ranganathan of El Dorado Hills CA (US)|Vasanth Ranganathan of El Dorado Hills CA (US)]][[Category:Vasanth Ranganathan of El Dorado Hills CA (US)]]

[[:Category:James Valerio of North Plains OR (US)|James Valerio of North Plains OR (US)]][[Category:James Valerio of North Plains OR (US)]]

[[:Category:Jeffery S. Boles of Folsom CA (US)|Jeffery S. Boles of Folsom CA (US)]][[Category:Jeffery S. Boles of Folsom CA (US)]]

[[:Category:Hema Chand Nalluri of Bengaluru (IN)|Hema Chand Nalluri of Bengaluru (IN)]][[Category:Hema Chand Nalluri of Bengaluru (IN)]]

[[:Category:Aditya Navale of Folsom CA (US)|Aditya Navale of Folsom CA (US)]][[Category:Aditya Navale of Folsom CA (US)]]

[[:Category:Ben J. Ashbaugh of Folsom CA (US)|Ben J. Ashbaugh of Folsom CA (US)]][[Category:Ben J. Ashbaugh of Folsom CA (US)]]

[[:Category:Michal Mrozek of Gdansk (PL)|Michal Mrozek of Gdansk (PL)]][[Category:Michal Mrozek of Gdansk (PL)]]

[[:Category:Murali Ramadoss of Folsom CA (US)|Murali Ramadoss of Folsom CA (US)]][[Category:Murali Ramadoss of Folsom CA (US)]]

[[:Category:Hong Jiang of Los Altos CA (US)|Hong Jiang of Los Altos CA (US)]][[Category:Hong Jiang of Los Altos CA (US)]]

[[:Category:Ankur Shah of Folsom CA (US)|Ankur Shah of Folsom CA (US)]][[Category:Ankur Shah of Folsom CA (US)]]

==CONCURRENT COMPUTE CONTEXT - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17884755 titled 'CONCURRENT COMPUTE CONTEXT

==Simplified Explanation==

- System of concurrent compute queues for scheduling compute contexts on graphics processor hardware
- Apparatus includes system interface and general-purpose graphics processor
- Graphics processor has multiple hardware resources partitioned into isolated partitions
- Each partition includes command streamers and circuitry for scheduling compute workloads
- Workloads are submitted to command queues associated with command streamers

== Potential Applications ==
- High-performance computing
- Artificial intelligence and machine learning
- Scientific simulations and modeling
- Virtual reality and augmented reality applications

== Problems Solved ==
- Efficient scheduling of compute workloads on graphics processor hardware
- Simultaneous execution of a large number of compute contexts
- Partitioning of hardware resources for isolation and improved performance

== Benefits ==
- Increased performance and throughput for compute-intensive tasks
- Scalability for handling a large number of compute contexts simultaneously
- Flexibility in partitioning hardware resources for different workloads
- Enhanced capabilities for graphics processing and general-purpose computing


==Original Abstract Submitted==

Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.



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