View source for 17831311. PRE-DECODER CIRCUITRY simplified abstract (Micron Technology, Inc.)

=PRE-DECODER CIRCUITRY=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Vijayakrishna J. Vankayala of Allen TX (US)|Vijayakrishna J. Vankayala of Allen TX (US)]][[Category:Vijayakrishna J. Vankayala of Allen TX (US)]]

[[:Category:Hari Giduturi of Folsom CA (US)|Hari Giduturi of Folsom CA (US)]][[Category:Hari Giduturi of Folsom CA (US)]]

[[:Category:Jeffrey E. Koelling of Fairview TX (US)|Jeffrey E. Koelling of Fairview TX (US)]][[Category:Jeffrey E. Koelling of Fairview TX (US)]]

[[:Category:Mingdong Cui of Folsom CA (US)|Mingdong Cui of Folsom CA (US)]][[Category:Mingdong Cui of Folsom CA (US)]]

[[:Category:Ramachandra Rao Jogu of McKinney TX (US)|Ramachandra Rao Jogu of McKinney TX (US)]][[Category:Ramachandra Rao Jogu of McKinney TX (US)]]

==PRE-DECODER CIRCUITRY - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17831311 titled 'PRE-DECODER CIRCUITRY

==Simplified Explanation==

The present disclosure describes a technology called pre-decoder circuitry, which is used in memory arrays to select specific memory cells for operation. The pre-decoder circuitry includes a combination of transistors and bias conditions to provide selection signals to the memory cells.

* The pre-decoder circuitry includes a memory array with multiple memory cells.
* The decoder circuitry is connected to the memory array and consists of a p-type transistor, a first n-type transistor, and a second n-type transistor.
* The pre-decoder circuitry is designed to provide a bias condition to the gates of the transistors, which determines the selection signal for the memory cells.
* In a positive configuration, the bias condition sets the first gate, second gate, and third gate to zero volts, providing a selection signal to a specific memory cell.
* In a negative configuration, the bias condition sets the third gate to a negative voltage and the first gate and second gate to zero volts, providing a selection signal to a different memory cell.

Potential applications of this technology:

* Memory arrays in electronic devices such as computers, smartphones, and tablets.
* Any application that requires efficient and accurate selection of specific memory cells.

Problems solved by this technology:

* Efficient selection of specific memory cells in a memory array.
* Accurate and reliable operation of memory cells.

Benefits of this technology:

* Improved performance and efficiency of memory arrays.
* Enhanced reliability and accuracy in memory cell selection.
* Simplified circuitry design for memory arrays.


==Original Abstract Submitted==

The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.



[[Category:G11C13/00]]