View source for 17823644. Backside Contacts for Signal Routing simplified abstract (Apple Inc.)

=Backside Contacts for Signal Routing=


==Organization Name==

[[:Category:Apple Inc.|Apple Inc.]]


[[Category:Apple Inc.]]

==Inventor(s)==

[[:Category:Emre Alptekin of Santa Clara CA (US)|Emre Alptekin of Santa Clara CA (US)]][[Category:Emre Alptekin of Santa Clara CA (US)]]

[[:Category:Antonietta Oliva of Sausalito CA (US)|Antonietta Oliva of Sausalito CA (US)]][[Category:Antonietta Oliva of Sausalito CA (US)]]

==Backside Contacts for Signal Routing - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17823644 titled 'Backside Contacts for Signal Routing

==Simplified Explanation==

The patent application discloses a cell layout for FinFET devices or other FET devices utilizing an isolation gate structure for routing between a signal input of an active gate and a backside metal layer.

* Isolation gate structure includes a metal fill surrounded by gate spacers.
* Metal fill connects between the topside layers and the backside layer in the device.
* Metal fill can be connected to the signal input of the active gate through routing in a topside metal layer or a metal wire in a topside insulating layer.
* Isolation gate structure can be part of any standard cell placed at a cell boundary or inside the cell for backside signal routing.
* Filler cells with isolation gate structures can provide backside routing connections for adjacent functional cells.

Potential applications of this technology:
* Integrated circuits
* Semiconductor devices
* Electronic devices

Problems solved by this technology:
* Efficient routing between signal inputs and backside metal layers
* Improved connectivity within FET devices
* Enhanced functionality of standard cells

Benefits of this technology:
* Enhanced performance of FinFET devices
* Increased flexibility in cell layout design
* Improved signal routing efficiency


==Original Abstract Submitted==

A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an isolation gate structure to provide routing between a signal input of an active gate and a backside metal layer. The isolation gate structure includes a metal fill surrounded by gate spacers. The metal fill connects between the topside layers in the device and the backside layer in the device. The metal fill may be connected to the signal input of the active gate through routing either in a topside metal layer or a metal wire placed in a topside insulating layer. The isolation gate structure can be part of any standard cell being placed at a cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with isolation gate structures may provide backside routing connections for adjacent functional cells.



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