View source for 17817143. MEMORY AND FORMING METHOD THEREOF simplified abstract (Changxin Memory Technologies, Inc.)

=MEMORY AND FORMING METHOD THEREOF=


==Organization Name==

[[:Category:Changxin Memory Technologies, Inc.|Changxin Memory Technologies, Inc.]]


[[Category:Changxin Memory Technologies, Inc.]]

==Inventor(s)==

[[:Category:Yi Tang of Hefei City (CN)|Yi Tang of Hefei City (CN)]][[Category:Yi Tang of Hefei City (CN)]]

==MEMORY AND FORMING METHOD THEREOF - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17817143 titled 'MEMORY AND FORMING METHOD THEREOF

==Simplified Explanation==

The present disclosure describes a method for forming a memory using a stacked layer on a substrate. The stacked layer includes interlayer isolation layers and a sacrificial layer group. The method includes the following steps:

* Forming a stacked layer on a substrate surface, with interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent interlayer isolation layers. The sacrificial layer group consists of a first, second, and third sacrificial layer stacked sequentially in the first direction. The stacked layer also includes a transistor region.
* Removing the second sacrificial layer in the transistor region to create a first gap.
* Forming a gate layer and a channel layer that wraps around the gate layer in the first gap.

Potential applications of this technology include:

* Memory devices: The method described can be used to form memory devices with improved performance and reliability.
* Integrated circuits: The method can be applied to the fabrication of integrated circuits, enabling the production of smaller and more efficient devices.

Problems solved by this technology include:

* Improved performance: The method allows for the formation of memory devices with enhanced performance characteristics, such as faster read and write speeds.
* Increased reliability: The use of interlayer isolation layers and sacrificial layers helps to reduce the risk of short circuits and other electrical failures.

Benefits of this technology include:

* Simplified fabrication process: The method simplifies the process of forming a memory by utilizing a stacked layer structure and sacrificial layers.
* Enhanced device performance: The resulting memory devices exhibit improved performance and reliability compared to conventional methods.
* Cost-effective production: The method can be implemented using existing manufacturing techniques, making it a cost-effective solution for memory production.


==Original Abstract Submitted==

The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the second sacrificial layer in the transistor region to form a first gap; and forming a gate layer and a channel layer wrapping the gate layer in the first gap.



[[Category:H01L27/108]]