View source for 17546677. USER-LEVEL THREADING FOR SIMULATING MULTI-CORE PROCESSOR simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

=USER-LEVEL THREADING FOR SIMULATING MULTI-CORE PROCESSOR=


==Organization Name==

[[:Category:INTERNATIONAL BUSINESS MACHINES CORPORATION|INTERNATIONAL BUSINESS MACHINES CORPORATION]]


[[Category:INTERNATIONAL BUSINESS MACHINES CORPORATION]]

==Inventor(s)==

[[:Category:Hiroshi Inoue of Tokyo (JP)|Hiroshi Inoue of Tokyo (JP)]][[Category:Hiroshi Inoue of Tokyo (JP)]]

==USER-LEVEL THREADING FOR SIMULATING MULTI-CORE PROCESSOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17546677 titled 'USER-LEVEL THREADING FOR SIMULATING MULTI-CORE PROCESSOR

==Simplified Explanation==

The abstract describes a method for improving the execution speed of a multi-core simulator by selecting specific layers in the hierarchical architecture to simulate on different OS threads. The method also includes executing parallel simulations of units within the selected layers that frequently communicate with each other.

* The method improves the execution speed of a multi-core simulator.
* The simulator simulates a target multi-core processor with a hierarchical architecture.
* The hierarchical architecture includes multiple corelets per core, which in turn include multiple functional units.
* The simulator is implemented using multiple OS threads.
* The method selects layers in the hierarchical architecture to simulate on one of the OS threads.
* The selection is based on a shortest estimated layer execution time formula.
* The formula takes into account the number of cores in the simulator, the number of OS threads, and a threading overhead coefficient.
* The method executes a parallel simulation of units within the selected layers that frequently communicate with each other.
* Each unit is assigned a user-level thread for simulation.

Potential applications of this technology:

* Improving the performance of multi-core simulators.
* Enhancing the accuracy of simulations for hierarchical multi-core processors.
* Optimizing the execution speed of simulations for target multi-core processors.

Problems solved by this technology:

* Slow execution speed of multi-core simulators.
* Inefficient simulation of hierarchical multi-core processors.
* Difficulty in accurately simulating units that frequently communicate with each other.

Benefits of this technology:

* Faster execution speed of multi-core simulators.
* More accurate simulations for hierarchical multi-core processors.
* Improved efficiency in simulating units with frequent communication.


==Original Abstract Submitted==

A method improves an execution speed of a host multi-core simulator simulating a target multi-core processor that has a hierarchical architecture including multiple corelets per core that, in turn include multiple functional units. The host multi-core simulator is implemented using multiple OS threads. The method selects layers in the hierarchical architecture to simulate on one of the OS threads, based on a shortest estimated layer execution time determined by (1.0+t/c*s)/min(c, t), wherein c is a number of cores in the simulator, t is a number of OS threads, and s is a threading overhead coefficient. The method respectively executes, from among the selected layers, a parallel simulation of the units therein that frequently communicate with each other on one of the multiple OS threads based on a communication frequency threshold, by assigning and using a respective user-level thread for each of the units from among a plurality of user-level threads.



[[Category:G06F9/48]]