View source for 17531966. NON-SELF-ALIGNED WRAP-AROUND CONTACT IN A TIGHT GATE PITCHED TRANSISTOR simplified abstract (International Business Machines Corporation)

=NON-SELF-ALIGNED WRAP-AROUND CONTACT IN A TIGHT GATE PITCHED TRANSISTOR=


==Organization Name==

[[:Category:International Business Machines Corporation|International Business Machines Corporation]]


[[Category:International Business Machines Corporation]]

==Inventor(s)==

[[:Category:Chanro Park of Clifton Park NY (US)|Chanro Park of Clifton Park NY (US)]][[Category:Chanro Park of Clifton Park NY (US)]]

[[:Category:Ruilong Xie of Niskayuna NY (US)|Ruilong Xie of Niskayuna NY (US)]][[Category:Ruilong Xie of Niskayuna NY (US)]]

[[:Category:Kangguo Cheng of Schenectady NY (US)|Kangguo Cheng of Schenectady NY (US)]][[Category:Kangguo Cheng of Schenectady NY (US)]]

[[:Category:Juntao Li of Cohoes NY (US)|Juntao Li of Cohoes NY (US)]][[Category:Juntao Li of Cohoes NY (US)]]

==NON-SELF-ALIGNED WRAP-AROUND CONTACT IN A TIGHT GATE PITCHED TRANSISTOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17531966 titled 'NON-SELF-ALIGNED WRAP-AROUND CONTACT IN A TIGHT GATE PITCHED TRANSISTOR

==Simplified Explanation==

The abstract describes an integrated circuit (IC) that includes a shared source or drain (S/D) region between two channels. The shared S/D region has a recessed second surface and sidewalls, and is wrapped around by a contact. The IC also includes gate structures on the channels.

* The IC includes a shared source or drain (S/D) region between two channels.
* The shared S/D region has a recessed second surface and sidewalls.
* The IC includes gate structures on the channels.
* A contact wraps around the shared S/D region at the exterior of the recess.

Potential applications of this technology:
* Integrated circuits and electronic devices that require efficient and reliable connections between channels and shared S/D regions.

Problems solved by this technology:
* Provides a contact structure that allows for improved electrical connections between channels and shared S/D regions.
* Helps to prevent leakage and improve performance in integrated circuits.

Benefits of this technology:
* Improved electrical connections between channels and shared S/D regions.
* Enhanced performance and reduced leakage in integrated circuits.
* Enables the design and development of more efficient and reliable electronic devices.


==Original Abstract Submitted==

An integrated circuit (IC) is provided. The IC includes a substrate that includes first and second channels. A shared source or drain (S/D) region is between the first and second channels. The shared source or drain region includes an uppermost surface and further includes a second surface recessed from the uppermost surface and sidewalls extending from the uppermost surface to the second surface to define a recess. First and second gate structures including gate metal are disposed on the first and second channels. An S/D wrap-around contact (WAC) includes a first portion which extends into the recess to contact the second surface and the sidewalls and is wrapped around the S/D region at an exterior of the recess.



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