View source for 17524062. VERTICAL TRANSISTORS HAVING IMPROVED CONTROL OF PARASITIC CAPACITANCE AND GATE-TO-CONTACT SHORT CIRCUITS simplified abstract (International Business Machines Corporation)

=VERTICAL TRANSISTORS HAVING IMPROVED CONTROL OF PARASITIC CAPACITANCE AND GATE-TO-CONTACT SHORT CIRCUITS=


==Organization Name==

[[:Category:International Business Machines Corporation|International Business Machines Corporation]]


[[Category:International Business Machines Corporation]]

==Inventor(s)==

[[:Category:ChoongHyun Lee of Chigasaki (JP)|ChoongHyun Lee of Chigasaki (JP)]][[Category:ChoongHyun Lee of Chigasaki (JP)]]

[[:Category:Ardasheir Rahman of Schenectady NY (US)|Ardasheir Rahman of Schenectady NY (US)]][[Category:Ardasheir Rahman of Schenectady NY (US)]]

[[:Category:Xin Miao of San Jose CA (US)|Xin Miao of San Jose CA (US)]][[Category:Xin Miao of San Jose CA (US)]]

[[:Category:Brent A. Anderson of Jericho VT (US)|Brent A. Anderson of Jericho VT (US)]][[Category:Brent A. Anderson of Jericho VT (US)]]

[[:Category:Alexander Reznicek of Troy NY (US)|Alexander Reznicek of Troy NY (US)]][[Category:Alexander Reznicek of Troy NY (US)]]

==VERTICAL TRANSISTORS HAVING IMPROVED CONTROL OF PARASITIC CAPACITANCE AND GATE-TO-CONTACT SHORT CIRCUITS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17524062 titled 'VERTICAL TRANSISTORS HAVING IMPROVED CONTROL OF PARASITIC CAPACITANCE AND GATE-TO-CONTACT SHORT CIRCUITS

==Simplified Explanation==

The abstract describes a method of forming an integrated circuit (IC) by performing fabrication operations that include forming a channel fin and a gate structure. The gate structure has an L-shape profile with a conductive gate foot region, which is replaced with a dielectric foot region.

* The method involves fabricating an IC by forming a channel fin and a gate structure.
* The gate structure has an L-shape profile, with a conductive gate foot region.
* The conductive gate foot region is replaced with a dielectric foot region.

Potential Applications:
* This technology can be applied in the semiconductor industry for the fabrication of integrated circuits.
* It can be used in the production of various electronic devices, such as smartphones, computers, and other consumer electronics.

Problems Solved:
* The method solves the problem of reducing leakage current in integrated circuits.
* It addresses the issue of improving the performance and efficiency of electronic devices.

Benefits:
* By replacing the conductive gate foot region with a dielectric foot region, the method reduces leakage current in the IC.
* This leads to improved performance and energy efficiency of electronic devices.
* The method provides a more reliable and stable operation of integrated circuits.


==Original Abstract Submitted==

Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC. The fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region.



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