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Category:Gilbert Dewey of Beaverton OR (US)
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Pages in category "Gilbert Dewey of Beaverton OR (US)"
The following 15 pages are in this category, out of 15 total.
1
- 17523711. CLADDING AND CONDENSATION FOR STRAINED SEMICONDUCTOR NANORIBBONS simplified abstract (Intel Corporation)
- 17847625. SPUTTER TARGETS AND SOURCES FOR SELF-DOPED SOURCE AND DRAIN CONTACTS simplified abstract (Intel Corporation)
- 17847628. LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES simplified abstract (Intel Corporation)
- 17850782. SIGE:GAB SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY simplified abstract (Intel Corporation)
- 18216490. SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS (Intel Corporation)
- 18419015. SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES simplified abstract (Intel Corporation)
- 18540544. TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN simplified abstract (Intel Corporation)
- 18614290. STACKED FORKSHEET TRANSISTORS simplified abstract (Intel Corporation)
- 18757013. CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES simplified abstract (Intel Corporation)
I
- Intel corporation (20240105852). TOP-GATE DOPED THIN FILM TRANSISTOR simplified abstract
- Intel corporation (20240113161). TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN simplified abstract
- Intel corporation (20240162141). SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES simplified abstract
- Intel corporation (20240186127). SPUTTER TARGETS FOR SELF-DOPED SOURCE AND DRAIN CONTACTS simplified abstract
- Intel corporation (20240234422). STACKED FORKSHEET TRANSISTORS simplified abstract
- Intel corporation (20240347610). CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES simplified abstract