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Category:Ehren Mannebach of Beaverton OR (US)
Pages in category "Ehren Mannebach of Beaverton OR (US)"
The following 8 pages are in this category, out of 8 total.
1
- 18419015. SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES simplified abstract (Intel Corporation)
- 18513028. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING SELECTIVE BOTTOM-UP APPROACH simplified abstract (Intel Corporation)
- 18614290. STACKED FORKSHEET TRANSISTORS simplified abstract (Intel Corporation)
- 18757013. CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES simplified abstract (Intel Corporation)
I
- Intel corporation (20240162141). SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES simplified abstract
- Intel corporation (20240234422). STACKED FORKSHEET TRANSISTORS simplified abstract
- Intel corporation (20240332379). BACKSIDE CONTACT ETCH BEFORE CAVITY SPACER FORMATION FOR BACKSIDE CONTACT OF TRANSISTOR SOURCE/DRAIN simplified abstract
- Intel corporation (20240347610). CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES simplified abstract