View source for Qualcomm incorporated (20250130801). PROCESSING UNIT EMPLOYING MICRO-OPERATIONS (MICRO-OPS) RANDOM ACCESS MEMORY (RAM) AS MAIN PROGRAM MEMORY

=PROCESSING UNIT EMPLOYING MICRO-OPERATIONS (MICRO-OPS) RANDOM ACCESS MEMORY (RAM) AS MAIN PROGRAM MEMORY=


==Organization Name==

[[:Category:qualcomm incorporated|qualcomm incorporated]]


[[Category:qualcomm incorporated]]

==Inventor(s)==

[[:Category:Shekhar Yeshwant Borkar of Beaverton OR US|Shekhar Yeshwant Borkar of Beaverton OR US]][[Category:Shekhar Yeshwant Borkar of Beaverton OR US]]

[[:Category:Nitin Yeshwant Borkar of Redmond WA US|Nitin Yeshwant Borkar of Redmond WA US]][[Category:Nitin Yeshwant Borkar of Redmond WA US]]

[[:Category:Rishi Khan of Wilmington DE US|Rishi Khan of Wilmington DE US]][[Category:Rishi Khan of Wilmington DE US]]

==PROCESSING UNIT EMPLOYING MICRO-OPERATIONS (MICRO-OPS) RANDOM ACCESS MEMORY (RAM) AS MAIN PROGRAM MEMORY==


This abstract first appeared for US patent application 20250130801 titled 'PROCESSING UNIT EMPLOYING MICRO-OPERATIONS (MICRO-OPS) RANDOM ACCESS MEMORY (RAM) AS MAIN PROGRAM MEMORY

==Original Abstract Submitted==

aspects disclosed in the detailed description include a processing unit (pu) employing micro-operations (micro-ops) random access memory (ram) as main program memory. the micro-ops ram comprises row circuits each associated with a micro-op and configured to store control signal parameters and output ports configured to be coupled to a register file and one or more execution units. in contrast to fetching and decoding instructions of an isa in a conventional pu, the processing unit loads a main program comprising micro-ops into the row circuits of the micro-ops ram. when executing an individual micro-op of the main program, the processing unit activates a row circuit in the micro-ops ram to cause its stored control signal parameters to be communicated through the output ports of the micro-ops ram to the register file and/or the one or more execution units and avoids the need for a decoding stage circuit, advantageously decreasing processing latency.



[[Category:G06F9/30]]
[[Category:CPC_G06F9/30043]]