View source for Taiwan semiconductor manufacturing company, ltd. (20250006257). MEMORY DEVICE AND DATA LATCHING METHOD

=MEMORY DEVICE AND DATA LATCHING METHOD=


==Organization Name==

[[:Category:taiwan semiconductor manufacturing company, ltd.|taiwan semiconductor manufacturing company, ltd.]]


[[Category:taiwan semiconductor manufacturing company, ltd.]]

==Inventor(s)==

[[:Category:Sanjeev Kumar Jain of OTTAWA (CA)|Sanjeev Kumar Jain of OTTAWA (CA)]][[Category:Sanjeev Kumar Jain of OTTAWA (CA)]]

==MEMORY DEVICE AND DATA LATCHING METHOD==


This abstract first appeared for US patent application 20250006257 titled 'MEMORY DEVICE AND DATA LATCHING METHOD




==Original Abstract Submitted==

a memory cell is configured to store data and operate in an operational state or a sleep state. a first set of transistors is configured to transfer data from the data sensing node of the memory cell to a data latch node, in response to the memory cell being in the operational state. a second set of transistors is configured to latch the data at the data latch node, in response to the memory cell being in the operational state. a third set of transistors is configured to latch the data at the data latch node, in response to the memory cell being in the sleep state. the first set of transistors is further configured to transfer the data from the data latch node to the data sensing node of the memory cell, in response to the memory cell being transitioned from the sleep state to the operational state.



[[Category:G11C11/419]]
[[Category:CPC_G11C11/419]]