US Patent Application 18448891. DATA PROCESSING CIRCUITRY AND METHOD, AND SEMICONDUCTOR MEMORY simplified abstract

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DATA PROCESSING CIRCUITRY AND METHOD, AND SEMICONDUCTOR MEMORY

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Yinchuan Gu of Hefei (CN)

DATA PROCESSING CIRCUITRY AND METHOD, AND SEMICONDUCTOR MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18448891 titled 'DATA PROCESSING CIRCUITRY AND METHOD, AND SEMICONDUCTOR MEMORY

Simplified Explanation

The patent application describes a data processing circuitry that includes a preprocessing circuit and a drive circuit.

  • The preprocessing circuit receives an initial data signal and generates a data signal to be processed and an auxiliary data signal based on the initial data signal.
  • The drive circuit is connected to the preprocessing circuit and performs several adjustments to generate a target data signal.
  • The drive circuit adjusts an initial calibration code based on a preset scenario to obtain a target calibration code.
  • The drive circuit also adjusts the value of a drive resistance based on the target calibration code.
  • Additionally, the drive circuit adjusts the drive capability of the data signal to be processed based on the auxiliary data signal and the adjusted drive resistance.
  • The result is the generation of a target data signal with improved accuracy and performance.


Original Abstract Submitted

A data processing circuitry includes: a preprocessing circuit, configured to receive an initial data signal and generate a data signal to be processed and an auxiliary data signal according to the initial data signal; and a drive circuit, connected with the preprocessing circuit and configured to: adjust an initial calibration code according to a preset scenario, to obtain a target calibration code; adjust a value of a drive resistance of the drive circuit according to the target calibration code; and adjust a drive capability of the data signal to be processed according to the auxiliary data signal and the adjusted drive resistance, to generate a target data signal.

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