US Patent Application 18448032. FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME simplified abstract
Contents
FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chen-Hao Huang of Hsinchu (TW)
Chien-Chang Lee of Hsinchu (TW)
FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18448032 titled 'FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME
Simplified Explanation
- The patent application describes a method of making a chip. - The method involves depositing a layer of polysilicon on both the top and bottom surfaces of a substrate. - The polysilicon layer is then patterned to create a recess, and the recess is completely cleared of the polysilicon layer. - Dopants are implanted into the substrate to create an implant region. - A contact etch stop layer (CESL) is deposited in the recess, covering the implant region. - The CESL is then patterned to create a CESL block. - A waveguide and a grating are formed in the substrate. - An interconnect structure is formed over the waveguide, grating, and CESL block. - The interconnect structure is etched to create a cavity that aligns with the grating.
Original Abstract Submitted
A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.
