US Patent Application 18447979. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME simplified abstract

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METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Te-Hsin Chiu of Hsinchu (TW)]]

[[Category:Shih-Wei Peng of Hsinchu (TW)]]

[[Category:Jiann-Tyng Tzeng of Hsinchu (TW)]]

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447979 titled 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME

Simplified Explanation

The patent application describes a method for manufacturing a semiconductor device.

  • The method involves creating a layout diagram that includes active area patterns and gate patterns.
  • The active area patterns are located near the boundary between two adjacent cells.
  • The gate patterns intersect with the active area patterns.
  • The method selects gate patterns based on their distance from a via-to-gate pattern and a cut-gate section.
  • The selected gate patterns have a distance greater than or equal to a reference value.
  • For each selected gate pattern, the size of the corresponding cut-gate section is set relative to a first size.
  • The first size is adjusted to prevent an overhang of a gate remnant portion extending towards the boundary.
  • The second size is determined to ensure the overhang is smaller than the first length.


Original Abstract Submitted

A method (of manufacturing a semiconductor device) includes generating a corresponding layout diagram including: regarding first and second active area patterns which (1) are correspondingly nearest to a boundary between, and (2) are correspondingly in, first and second abutting cells, and for each gate pattern that intersects the first or second active area pattern, selecting the gate patterns for which a first distance from a nearest corresponding via-to-gate (VG) pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each selected gate pattern, relative to a first size, setting a size of a corresponding cut-gate section to a second size; the first size otherwise resulting in an overhang of a gate remnant portion extending towards the boundary by a first length; and the second size resulting in the overhang extending by a second length smaller than the first length.

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