US Patent Application 18447685. PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT simplified abstract
Contents
PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447685 titled 'PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT
Simplified Explanation
The patent application describes a semiconductor structure that includes a substrate with two active regions.
- The first active region is located in one part of the substrate, while the second active region is located in another part.
- The structure includes multiple gate structures over each active region.
- Each gate structure consists of a gate stack with a high-k gate dielectric, a gate electrode, and gate spacers.
- The gate structures over the second active region also contain dopants in a portion of the gate electrode.
- The purpose of this structure is not explicitly mentioned in the abstract.
Original Abstract Submitted
A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.
