US Patent Application 18447483. SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES simplified abstract

SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chih-Ching Wang of Kinmen County (TW)

Wen-Yuan Chen of Taoyuan County (TW)

Wen-Hsing Hsieh of Hsinchu City (TW)

Kuan-Lun Cheng of Hsin-Chu (TW)

Chung-Wei Wu of Hsin-Chu County (TW)

Zhiqiang Wu of Hsinchu County (TW)

SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447483 titled 'SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES

Simplified Explanation

The patent application describes a method for manufacturing a semiconductor substrate with a fin structure. Here are the key points:

• The method starts with receiving a semiconductor substrate with a fin structure on its top surface.
• The fin structure is recessed to create source/drain trenches.
• A first dielectric layer is formed over the recessed fin structure in the trenches.
• A dopant element is implanted into a portion of the fin structure beneath the trenches to create an amorphous semiconductor layer.
• A second dielectric layer is formed over the recessed fin structure in the trenches.
• The semiconductor substrate is annealed to enhance its properties.
• The first and second dielectric layers are removed.
• The recessed fin structure is further recessed to provide a top surface.
• An epitaxial layer is formed on the top surface of the fin structure.

Overall, the method involves creating source/drain trenches, implanting a dopant, and forming dielectric layers before annealing and removing the layers. Finally, the fin structure is further recessed and an epitaxial layer is formed on top.

Original Abstract Submitted

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.