US Patent Application 18447344. SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION simplified abstract
Contents
SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==
[[Category:Te-Chih Hsiung of Taipei City (TW)]]
[[Category:I-Hung Li of New Taipei City (TW)]]
[[Category:Yi-Ruei Jhan of Hsinchu City (TW)]]
[[Category:Yuan-Tien Tu of Puzih City (TW)]]
SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447344 titled 'SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION
Simplified Explanation
- The patent application describes a method for improving the filling of interconnect structures in semiconductor devices. - The method involves etching and filling a first interconnect structure, then etching back a portion of it. - A second interconnect structure is then filled, along with the remaining portion of the first interconnect structure. - By removing a portion of the first interconnect structure before filling, the height of the remaining portion is closer to the height of the second interconnect structure. - This reduces the risk of the second interconnect structure closing before the first one is fully filled, which could result in the formation of a void.
Original Abstract Submitted
A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.
