US Patent Application 18447170. METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW simplified abstract
Contents
METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chung-Pin Chou of Hsinchu (TW)
Yan-Cheng Chen of Hsinchu (TW)
METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447170 titled 'METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW
Simplified Explanation
- The patent application describes a system for detecting defects in semiconductor wafers. - The system captures test images of the semiconductor wafer. - These test images are then analyzed using a machine learning process. - An analysis model, trained with the machine learning process, generates simulated integrated circuit layouts based on the test images. - The system compares these simulated layouts to reference integrated circuit layouts to detect defects in the semiconductor wafer.
Original Abstract Submitted
A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.
