US Patent Application 18446998. Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof simplified abstract

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Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chun-An Lin of Tainan City (TW)

Kuo-Pi Tseng of Hsinchu (TW)

Tzu-Chieh Su of Hsinchu (TW)

Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446998 titled 'Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof

Simplified Explanation

The patent application describes techniques for forming source and drain regions in FinFETs to reduce channel resistance and drain-induced barrier lowering (DIBL).

  • The method involves a three-step etch process to create a recess in the source/drain region of a fin.
  • The first anisotropic etch and isotropic etch are adjusted to determine the location of the source/drain tip.
  • The depth of the recess after the first etches is less than the desired depth.
  • The second anisotropic etch is then used to extend the depth of the recess to the target depth.
  • The source/drain tip is positioned near the top of the fin to minimize channel resistance.
  • The bottom portion of the recess is spaced away from the gate footing to reduce DIBL.
  • The recess is filled with an epitaxial semiconductor material.


Original Abstract Submitted

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

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