US Patent Application 18446918. SEMICONDUCTOR DEVICE AND METHOD simplified abstract

SEMICONDUCTOR DEVICE AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chunchieh Wang of Kaohsiung City (TW)

Yueh-Ching Pai of Taichung City (TW)

SEMICONDUCTOR DEVICE AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446918 titled 'SEMICONDUCTOR DEVICE AND METHOD

Simplified Explanation

The patent application describes a device with nanostructures on a substrate, including a first set and a second set of nanostructures, each with a channel region.

• The device also includes a gate dielectric layer that wraps around both sets of nanostructures.
• A first work function tuning layer is placed on the gate dielectric layer of the first set of nanostructures, wrapping around each of them.
• A glue layer is then added on top of the first work function tuning layer, also wrapping around each of the first set of nanostructures.
• A second work function tuning layer is applied on top of the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures.
• Finally, a fill layer is added on top of the second work function tuning layer.

Original Abstract Submitted

An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.