US Patent Application 18446664. ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS simplified abstract

ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Shi Ning Ju of Hsinchu City (TW)]]

[[Category:Kuo-Cheng Chiang of Hsinchu County (TW)]]

[[Category:Guan-Lin Chen of Hsinchu County (TW)]]

[[Category:Chih-Hao Wang of Hsinchu County (TW)]]

[[Category:Kuan-Lun Cheng of Hsin-Chu (TW)]]

ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446664 titled 'ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS

Simplified Explanation

The patent application describes a semiconductor structure with multiple layers on a substrate and a metal gate structure.

• The semiconductor structure includes a stack of semiconductor layers on a substrate.
• The metal gate structure is placed over and interleaved with the stack of semiconductor layers.
• The metal gate structure consists of a gate electrode on top of a gate dielectric layer.
• There is a first isolation structure next to one side of the stack of semiconductor layers.
• The gate dielectric layer fills the space between the first isolation structure and the first sidewall of the stack of semiconductor layers.
• There is a second isolation structure next to the other side of the stack of semiconductor layers.
• The gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Original Abstract Submitted

A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.