US Patent Application 18446648. Semiconductor Devices Including Decoupling Capacitors simplified abstract
Contents
Semiconductor Devices Including Decoupling Capacitors
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Hou-Yu Chen of Zhubei City (TW)
Ching-Wei Tsai of Hsinchu (TW)
Kuan-Lun Cheng of Hsinchu (TW)
Chung-Hui Chen of Hsinchu (TW)
Semiconductor Devices Including Decoupling Capacitors - A simplified explanation of the abstract
This abstract first appeared for US patent application 18446648 titled 'Semiconductor Devices Including Decoupling Capacitors
Simplified Explanation
The patent application describes methods of forming decoupling capacitors in interconnect structures on the backsides of semiconductor devices. These devices include a device layer with a transistor, interconnect structures on both the front and back sides, and a contact that connects to the source/drain region of the transistor.
- The second interconnect structure on the backside includes a first dielectric layer and a first conductive line connected to the source/drain region of the transistor.
- The second dielectric layer adjacent to the first conductive line has a high k-value (greater than 7.0), which allows for increased capacitance.
- The first conductive line and the second dielectric layer form a decoupling capacitor, which helps to stabilize the power supply voltage and reduce noise in the device.
- This innovation provides a more efficient and compact way of incorporating decoupling capacitors into semiconductor devices, improving their performance and reliability.
Original Abstract Submitted
Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.
