US Patent Application 18366981. Flip Flop Circuit simplified abstract

Flip Flop Circuit

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Po-Chia Lai of Fremont CA (US)]]

[[Category:Stefan Rusu of Sunnyvale CA (US)]]

Flip Flop Circuit - A simplified explanation of the abstract

This abstract first appeared for US patent application 18366981 titled 'Flip Flop Circuit

Simplified Explanation

The abstract describes a flip flop circuit that consists of several components: a first master portion, a second master portion, at least one determining portion, and a slave portion.

• The first master portion operates in a first mode and receives a first input, generating first master outputs.
• The second master portion operates in a second mode and receives a second input, generating second master outputs.
• The determining portion receives at least one enable signal and has determining inputs and determining outputs.
• The determining inputs are connected to the first master outputs and the second master outputs.
• The determining portion determines the determining outputs based on the enable signal, either being the first master outputs or the second master outputs.
• The slave portion receives the determining outputs and generates an output signal.

Bullet points:

• Flip flop circuit with multiple components: first master portion, second master portion, determining portion, and slave portion.
• First master portion operates in first mode, receives first input, and generates first master outputs.
• Second master portion operates in second mode, receives second input, and generates second master outputs.
• Determining portion receives enable signal and determines its outputs based on the enable signal.
• Determining inputs connected to first master outputs and second master outputs.
• Slave portion receives determining outputs and generates output signal.

Original Abstract Submitted

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.