US Patent Application 18363881. FUSI GATED DEVICE FORMATION simplified abstract

FUSI GATED DEVICE FORMATION

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Yi-Huan Chen of Hsin Chu City (TW)

Chien-Chih Chou of New Taipei City (TW)

Ta-Wei Lin of Minxiong Township (TW)

Hsiao-Chin Tuan of Taowan (TW)

Alexander Kalnitsky of San Francisco CA (US)

Kong-Beng Thei of Pao-Shan Village (TW)

Chia-Hong Wu of Taichung City (TW)

FUSI GATED DEVICE FORMATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18363881 titled 'FUSI GATED DEVICE FORMATION

Simplified Explanation

The patent application describes an integrated chip design with specific layers and structures.

• The chip includes a gate dielectric structure over a substrate.
• A metal layer is placed on top of the gate dielectric structure.
• A conductive layer is then placed on top of the metal layer.
• The conductive layer is in contact with a polysilicon layer on opposing sides.
• The bottom surface of the polysilicon layer is aligned with the bottom surface of the conductive layer.
• A dielectric layer is placed on top of the polysilicon layer.
• The dielectric layer extends continuously from the sidewalls of the polysilicon layer to the upper surface of the conductive layer.

Original Abstract Submitted

Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.