US Patent Application 18363192. DATA RETENTION CIRCUIT AND METHOD simplified abstract

DATA RETENTION CIRCUIT AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Kai-Chi Huang of Hsinchu (TW)]]

[[Category:Yung-Chen Chien of Hsinchu (TW)]]

[[Category:Chi-Lin Liu of Hsinchu (TW)]]

[[Category:Wei-Hsiang Ma of Hsinchu (TW)]]

[[Category:Jerry Chang Jui Kao of Hsinchu (TW)]]

[[Category:Shang-Chih Hsieh of Hsinchu (TW)]]

[[Category:Lee-Chung Lu of Hsinchu (TW)]]

DATA RETENTION CIRCUIT AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18363192 titled 'DATA RETENTION CIRCUIT AND METHOD

Simplified Explanation

The patent application describes a circuit that includes various components such as power nodes, reference nodes, latches, and level shifters.

• The circuit has a first power node with a certain voltage level, a second power node with a different voltage level, and a reference node with a reference voltage level.
• The circuit includes a master latch that produces a first bit based on a received bit, and a slave latch that produces a second bit based on the first bit and an output bit.
• There is also a first level shifter that generates a third bit based on a complementary bit pair, and a retention latch that includes a second level shifter and a pair of inverters to output the complementary bit pair based on the second bit.
• The slave latch and the first level shifter are connected between the first power and reference nodes, while the retention latch is connected between the second power and reference nodes.

Original Abstract Submitted

A circuit includes a first power node having a first voltage level, a second power node having a second voltage level different from the first voltage level, a reference node having a reference voltage level, a master latch that outputs a first bit based on a received bit, a slave latch that outputs a second bit based on the first bit and an output bit based on a selected one of the first bit or a third bit, a first level shifter that outputs the third bit based on a complementary bit pair, and a retention latch including a second level shifter and a pair of inverters that outputs the complementary bit pair based on the second bit. The slave latch and the first level shifter are coupled between the first power and reference nodes, and the retention latch is coupled between the second power and reference nodes.