US Patent Application 18363143. TEST CIRCUIT AND METHOD simplified abstract

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TEST CIRCUIT AND METHOD

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Hsieh-Hung Hsieh of Hsinchu (TW)

Yen-Jen Chen of Hsinchu (TW)

Tzu-Jin Yeh of Hsinchu (TW)

TEST CIRCUIT AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18363143 titled 'TEST CIRCUIT AND METHOD

Simplified Explanation

The abstract describes an integrated circuit (IC) that includes a device-under-test (DUT) which receives a first AC signal and outputs a second AC signal based on the first signal. The IC also includes two detection circuits.

  • The IC includes a device-under-test (DUT) that processes AC signals.
  • The DUT receives a first AC signal at a first node and outputs a second AC signal at a second node.
  • The second AC signal is derived from the first AC signal.
  • The IC includes two detection circuits.
  • Each detection circuit includes a first gain stage connected to either the first or second node through a capacitive device.
  • Each detection circuit also includes a second gain stage connected in a cascade arrangement with the first gain stage.
  • Each detection circuit further includes a low-pass filter that generates a DC signal based on the output of the second gain stage.
  • The low-pass filter removes high-frequency components from the output signal.
  • The DC signal can be used for further processing or analysis.


Original Abstract Submitted

An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage.

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