US Patent Application 18362934. METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT simplified abstract
Contents
METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Shih-Lien Linus Lu of Hsinchu (TW)
Sai-Hooi Yeong of Hsinchu (TW)
METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18362934 titled 'METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT
Simplified Explanation
- The patent application describes a method for testing a 3D memory cell array. - The method involves writing data to each layer of memory cells in the array. - A read operation is simultaneously performed on each memory cell in at least one pillar of the array. - The read operation helps determine if any memory cell in the array has failed. - If a memory cell is found to have failed, it is replaced with a spare memory cell. - The first pillar consists of memory cells on each corresponding layer of the array.
Original Abstract Submitted
A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.
