US Patent Application 18362889. IC DEVICE LAYOUT METHOD simplified abstract
Contents
IC DEVICE LAYOUT METHOD
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Hui-Zhong Zhuang of Hsinchu (TW)
Jiann-Tyng Tzeng of Hsinchu (TW)
IC DEVICE LAYOUT METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18362889 titled 'IC DEVICE LAYOUT METHOD
Simplified Explanation
- The patent application describes a method for generating an IC layout diagram. - The method involves overlapping a channel region and a gate region of a complementary field-effect transistor (CFET) in the IC layout. - This overlap defines a channel overlap region. - An isolation region is then positioned in the IC layout, encompassing the entire channel overlap region. - The isolation region is intersected with a conductive region. - Finally, an IC layout diagram is generated based on the IC layout. - The innovation of this method lies in the specific steps taken to define and position the channel overlap region and isolation region in the IC layout.
Original Abstract Submitted
A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.
