US Patent Application 18362248. ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES simplified abstract
Contents
ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Yu Lun Ke of Hsinchu City (TW)
Yu-Wei Kuo of Hsinchu City (TW)
Hung Jui Chang of Changhua County (TW)
ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18362248 titled 'ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
Simplified Explanation
The patent application describes a method for forming a semiconductor structure. Here are the key points:
- The method involves several steps to create the structure.
- First, an etch stop layer is formed on a substrate.
- Then, a metal oxide layer is formed on top of the etch stop layer.
- Next, an interlayer dielectric (ILD) layer is formed on the metal oxide layer.
- A trench etch opening is created over the ILD layer.
- A capping layer is formed over the trench etch opening.
- Finally, a via etch opening is created over the capping layer.
Overall, this method provides a process for creating a semiconductor structure with specific layers and openings.
Original Abstract Submitted
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
